FIG. 1 is a block diagram of a data output circuit for a semiconductor storage device incorporated herein to disclose the background art of this invention. As seen from FIG. 1, data are read from a memory cell 11 via bit lines N1 and N2. The data on the bit lines N1 and N2 are equalized by a bit line equalizing transistor Tr1. The bit line N1 is connected to a data line N3 via a column selecting transistor Tr11. The bit line N2 is connected to a data line N4 via a column selecting transistor Tr12. The transistors Tr11 and Tr12 are controlled by a control line N11 to turn on or off so that the bit lines N1 and N2 are connected to or disconnected from the data lines N3 and N4, respectively. To the control line N11, there is applied a decoded signal of an address signal. The data lines N3 and N4 are equalized by an input/output line equalizing transistor Tr2. The input/output lines N3 and N4 are connected to a first sense amplifier (differential amplifier) 21. All sense amplifiers in the following description are made of a differential amplifier whose data relationship is shown in FIG. 2. The outputs from the first sense amplifier 21 are delivered onto first sense amplifier output data lines N5 and N6. Between the first sense amplifier output data lines N5 and N6, there is connected a data line equalizing transistor Tr3. The outputs from the first sense amplifier 21 are equalized by the transistor Tr3. The data on the data lines N5 and N6 are inputted to a second sense amplifier 22. The outputs from the amplifier 22 are delivered to second sense amplifier output data lines N7 and N8. Between the data lines N5 and N7, there is connected an input/output shorting transistor Tr5. Between the data lines N6 and N8, there is connected an input/output shorting transistor Tr6. The transistors Tr5 and Tr6 operate to short the inputs and outputs of the second sense amplifier 22. The second sense amplifier output data lines N7 and N8 are connected to an output buffer amplifier 25 whose particular configuration is shown in FIG. 3. An output equalizing transistor Tr4 is connected between the data lines N7 and N8 on the input side of the output buffer amplifier 25, to equalize the data on the lines N7 and N8. There are connected to the output side of the output buffer amplifier 25, output buffer transistors Tr21 and Tr22. Data is outputted from the interconnection node of the transistors Tr21 and Tr22.
An equalizing pulse .PHI..sub.eq is supplied from an equalizing pulse generator circuit 40 to the gates of the transistors Tr1 to Tr6. The equalizing pulse generator circuit 40 is controlled by a detector circuit 30 which detects a change in address signal. The detector circuit 30 is constructed of input transition detector circuits 31, 32, . . . to which applied are addresses IN1, IN2, . . . , respectively. Each of the input transition detector circuits 31, 32, . . . has a circuit configuration such as shown in FIG. 4. Signal waveforms at various nodes of each of the circuits 31, 32, . . . are shown in FIG. 5. The relationship between the detector circuit 30 and equalizing pulse generator circuit 40 is shown in FIG. 6. The number of inverters IV in the circuit 40 depends upon the capacitance of a load connected to this circuit.
Next, the operation of the circuit shown in FIG. 1 will be described with reference to the timing chart shown in FIGS. 7 and 8 the difference between which is the width of a pulse shown in FIGS. 7(b) and 8(b). Referring to FIGS. 7 and 8, FIGS. 7(a) and 8(b) represent the transition state of address inputs IN1 and IN2, FIGS. 7(b) and 8(b) represent the equalizing pulse .PHI..sub.eq, FIGS. 7(c) and 8(c) represent the state of the first sense amplifier output data lines N5 and N6, FIGS. 7(d) and 8(d) represent the state of the second sense amplifier output data lines N7 and N8, and FIGS. 7(e) and 8(e) represent the state of an output (N9).
At time t1, addresses IN1, IN2, . . . transit. The input transition detector circuits 31, 32, detect address transition. The detected signal is supplied to the equalizing pulse generator circuit 40 which accordingly outputs the equalizing pulse .PHI..sub.eq as shown in FIG. 2(b) at time t2 in synchronization with the address change. This equalizing pulse .PHI..sub.eq causes the transistors Tr1 to Tr6 to turn on during the period from time t2 to t3. Namely, the transistor Tr1 is turned on to short the bit lines N1 and N2, the transistor Tr2 is turned on to short the data lines N3 and N4, the transistor Tr3 is turned on to short the data lines N5 and N6, and the transistor Tr4 is turned on to short the data lines N7 and N8. Accordingly, the pairs of data lines are made the same potential because of short-circuits. At the same time, the input/output shorting transistors Tr5 and Tr6 turn on to short the inputs and outputs of the second sense amplifier 22. Accordingly, the potentials of the outputs of the first and second sense amplifiers 21 and 22 take a certain potential V.sub.eq determined by the characteristics of transistors constituting the amplifiers, as shown in FIGS. 7(c) and 7(d). When the equalizing pulse .PHI..sub.eq falls down at time t3, the transistors Tr1 to Tr6 turn off. The data from the new memory cell selected by the new address are read via the bit lines N1 and N2, and column selecting transistors Tr11 and Tr12, to the data lines N3 and N4. The data are supplied via the first and second sense amplifiers 21 and 23, and output buffer amplifier 25 to the output buffer transistors Tr21 and Tr22. An output as shown in FIG. 7(e) is obtained at the output node N9.
With the above operation, data can be read from a memory cell without adversely affected by the contents of cell data at the preceding address.
In the above-described data output device, the equalizing pulse performs an equalization function as well as a function to inhibit data on the data lines to be transferred during the equalization operation. In order to read data from a memory cell at high speed, it is necessary to speed up the fall time of the equalizing pulse .PHI..sub.eq. It is necessary therefore (1) to make the pulse width of the equalizing pulse narrow or (2) to shorten the period from when an address transition is detected to when the equalizing pulse .PHI..sub.eq rises. However, if a sufficient equalizing effect is desired by using the equalizing pulse .PHI..sub.eq having a short pulse width, it becomes necessary to obtain a high conductance gm of the transistors Tr1 to Tr6, which generally results in an increase of the gate width of a MOS transistor and hence in an increase of the gate capacitance. The increase of the gate capacitance results in an increase of the load capacitance C(.PHI..sub.eq) connected to the equalizing pulse generating circuit 40. However in general, the number of stages of logical circuits (five stages of inverters IV in the case of FIG. 6) of the equalizing pulse generator circuit 40 is designed as small as possible to the extent that its load having the capacitance C(.PHI..sub.eq) can be driven without delay and the equalizing pulse .PHI..sub.eq can rise and fall at high speed. Because of this, the number of stages of logical circuits cannot be reduced. If the number of stages were reduced, the establishment of a pulse could be quickened but the load could not be driven sufficiently.
Apart from the above, there is another problem associated with the operation of the transistors Tr5 and Tr6 for shorting the inputs and outputs of the second sense amplifier 22. Specifically, upon establishment of the equalizing pulse .PHI..sub.eq, the transistors Tr5 and Tr6 short the inputs and inverted outputs of active elements of the second sense amplifier 22 so that the active elements enter a negative feedback operation. Therefore potentials at the inputs and outputs oscillate and converge to the potential V.sub.eq. If the width of the equalizing pulse .PHI..sub.eq is made shorter, this pulse may start terminating before the oscillation converges sufficiently. In this case, as shown in FIGS. 8(c) and 8(d), convergence of oscillation of the potentials at the data signal lines N5 and N6 is not satisfactory at time t3 when the equalizing pulse .PHI..sub.eq starts falling down. The second sense amplifier 22 therefore amplifies an insignificant potential difference between the data signal lines N5 and N6, resulting in a considerable read time delay. As seen from the foregoing description, it is necessary to set the width of the equalizing pulse .PHI..sub.eq to have a sufficient margin. The need to broaden the pulse width has been an obstacle against high speed data read.
As described above, the equalizing method for a data output device according to the background art does not provide stable data read at high speed, which has been a bottleneck for high system performance, especially for multi-bit systems having a number of data lines.